The present invention relates generally to the field of interrupt processing, and more particularly to validation of correctness of interrupt triggers and delivery.
Historically, a computer system or processor had only a single processor (aka processing unit or central processing unit). The processor included an instruction processing unit (IPU), a branch unit, a memory control unit and the like. Processors were later developed that incorporated multiple IPUs. Such processors were often referred to as multi-processors. Each such processor of a multi-processor computer system may include individual or shared caches, memory interfaces, system bus, address translation mechanism and the like. Virtual machine and instruction set architecture (ISA) emulators added a layer of software to a processor, that provided the virtual machine with multiple “virtual processors” by time-slice usage of a single IPU in a single hardware processor. As technology further evolved, multi-threaded processors were developed, enabling a single hardware processor having a single multi-thread IPU to provide a capability of simultaneously executing threads of different programs. Thus, each thread of a multi-threaded processor appeared to the operating system as a processor. As technology further evolved, it was possible to put multiple processors (each having an IPU) on a single semiconductor chip or die. These processors were referred to as processor cores or cores. Thus, terms such as processor, central processing unit, processing unit, microprocessor, core, processor core, processor thread, and thread, for example, are often used interchangeably.
The processor architecture of a computer system typically supports several types of interrupts. An interrupt is a notification given to the processor that causes the processor to halt the execution of code, such as operating code, and handle a condition that has arisen in the system or in one of the external devices of the system. As an example, when a key is pressed on the keyboard, an interrupt is passed to the processor from a peripheral controller. The interrupt causes the processor to momentarily stop its current execution stream and receive data from the peripheral controller. The interrupt causes overhead in the server processing unit due to the necessary context switch and latencies for bringing necessary interrupt code into a cache. Only then the processing unit can start actually processing the interrupt. The interrupt cause can be stored in one or more linked lists in memory in order to provide the processing unit with information on the interrupt cause.